By Koen Bertels (auth.), Koen Bertels (eds.)
HW/SW Co-Design for Heterogeneous Multi-Core systems describes the implications and end result of the FP6 undertaking which specializes in the improvement of an built-in device chain concentrating on a heterogeneous multi middle platform comprising of a normal objective processor (ARM or powerPC), a DSP (the diopsis) and an FPGA. The device chain takes latest resource code and proposes adjustments and mappings such that legacy code can simply be ported to a contemporary, multi-core platform. Downloadable software program can be supplied for simulation purposes.
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Extra info for Hardware/Software Co-design for Heterogeneous Multi-core Platforms: The hArtes Toolchain
The hArtes toolchain requires an XML architecture description, where main HW and SW characteristics are described. Beside the XML description (provided by the HW vendors), the toolchain uses source annotations via pragmas. From the developer point of view source annotations are optional because they are generated automatically by the toolchain. Both source and XML annotations can be used by the developer to tune the partitioning and mapping of the application. 1 XML Architecture Description File The XML Architecture Description File aims at providing a flexible specification of the target architecture and it is used for information exchange between the tools involved in the hArtes project.
NU-Tech distinguish between audio and video processing. This could be useful in a scenario where audio and video processing are performed by two different dedicated hardware. GAETool Overview The Graphical Algorithm Exploration Tool is a new feature of the NU-Tech Framework. Its main purpose is to produce a C description of an application designed in NU-Tech as a network of functional blocks (NUTSs) interconnected with each other and interacting with the PC inputs/outputs. The general overview of GAETool is shown in Fig.
The profile information is given for the GPP processor, which is the processor that contains the MASTER element in the architecture description file. Mapping Domain The mapping domain is used to instruct the backend compilers how tasks are mapped to different processing elements. We use two pragma directives: • generation pragmas, used to mark that, an implementation needs to be built for one particular functional component (like FPGA or DSP) • execution pragmas, used to indicate which functional component or which specific implementation a particular function is mapped for being executed.