By Siva G. Narendra, Anantha P. Chandrakasan
Covers intimately promising ideas on the equipment, circuit, and structure degrees of abstraction after first explaining the sensitivity of a number of the MOS leakage assets to those stipulations from the 1st ideas. additionally taken care of are the ensuing results so the reader is aware the effectiveness of leakage strength aid strategies lower than those diversified stipulations. Case stories provide real-world examples that take advantage of leakage strength relief strategies because the booklet highlights various gadget layout offerings that exist to mitigate raises within the leakage elements as expertise scales.
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Additional resources for Leakage in Nanometer CMOS Technologies (Integrated Circuits and Systems, Volume 1)
7% LowVt Avg. 5% Figure 2-17, Adder leakage reduction using the best input vector activation compared to the average and worst case standby leakage causing input vectors. 84 nJ Min. 4 uS Figure 2-18. Standby leakage power savings and the minimum time required in standby mode. 4 LEAKAGE REDUCTION USING FORCED STACKS As shown earlier, stacking of two transistors that are OFF has significantly reduced leakage compared to a single OFF transistor. However due to the iso-input load requirement and due to stacking of transistors, the drive current of a forced-stack gate will be lower resulting in increased delay.
The bouncing of the primary power rails of the chip affects all of its blocks. Any sensitive blocks with small noise margins can suffer spurious transitions or incorrect data as a result. One technique for reducing bouncing for the on-chip power nodes is to increase the gate-to-source voltage of a sleep transistor in a step-wise 3. Power Gating and Dynamic Voltage Scaling 47 manner. This gradual turn-on smoothes out the recharging of the nodes of the block leaving sleep. As a result, the current surge is reduced.
For the most basic implementation of power gating, the sleep transistors are the same type of device as the transistors that implement the functional part of the circuit. Turning off the sleep transistor provides leakage reduction for two primary reasons. First, the width of the sleep transistor usually is less than the total width of the transistors being gated. The smaller width provides a linear reduction in the total current drawn from the supply during standby. Secondly, leakage currents diminish whenever stacks of transistors are off due to the source biasing effect.